(1) Field of the Invention
The present invention relates to a process for making capacitor-under-bit-line dynamic random access memory (DRAM) device structures having an improved capacitor top electrode design. (The top electrode is also commonly referred to as top-plate electrode.) More specifically, the process employs a novel mask design and a sequence of novel process steps for improving the overlay margin between the bit-line contacts and the capacitors"" top electrodes. This method allows the capacitor top electrodes to be auto-self-aligned to the bit-line contacts for increased memory cell density.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronics industry for storing data. The DRAM circuit includes an array of memory cells, each cell consisting of a single capacitor and a single transfer transistor. Typically the transfer transistor is a field effect transistor (FET). Binary data (1""s and 0""s) are stored as charge on the capacitors, and the transfer transistor is used to retain the charge. During the read cycle the transfer transistor is used to interrogate the cell by means of bit lines. Two types of memory cells that are commonly used include a cell having a trench capacitor formed in the substrate under the FETs, and a cell having a stacked capacitor that is built over and between FETs. In the fabrication of DRAM circuits having stacked capacitors, the capacitor can be formed over the bit lines, and is commonly referred to as Capacitors-Over-Bit lines (COB), or can be formed under the bit lines, commonly referred to as Capacitors-Under-Bit lines (CUB). For all of the DRAM structures described above, the number of memory cells on a DRAM chip has increased dramatically over the years, and that number of cells is expected to exceed 1 Gigabit. This increase is a result of the downsizing of feature size of the discrete devices using improved high-resolution photolithography, improved directional plasma etching, and self-aligning techniques, with a resulting increase in circuit density.
Numerous methods of making these higher density DRAM devices have been reported. For example, Lee et al. in U.S. Pat. No. 6,165,839 describe a method for fabricating CUB DRAMs using a sidewall spacer to separate and self-align the tungsten bit line structure from the capacitor top electrode. U.S. Pat. No. 6,294,426 to Tu et al describes a method for making a CUB without increasing the aspect ratio of the bit-line contact opening. In U.S. Pat. No. 5,798,289 to Ajika, a method is described for making COB and therefore does not address the problem of making bit-line contact openings between adjacent capacitors that are required for CUB.
Although downscaling of devices and self-aligning techniques have dramatically increased the memory cell density on DRAM chips, there is still a strong need in the industry to further improve the structure and process to provide a more reliable process with further increases in cell density. More specifically, it is highly desirable to improve the overlay margins between the capacitor top electrodes and the bit-line contacts on capacitor-under-bit line DRAM chips.
A principal object of the present invention is to form an array of closely spaced DRAM cells, with increased overlay margins between capacitor top electrodes and bit-line contacts, resulting in increased memory cell density for Capacitor-Under-Bit line (CUB) DRAM circuits.
Another objective of this invention is to achieve the improved overlay margin by using a novel process resulting in auto-self-aligned capacitor top electrodes to the region where the bit-line contacts are formed.
This novel memory cell structure consists of an array of stacked capacitors under bit lines that have an improved overlay margin between the bit-line contacts and the capacitor top electrodes. The method for making the array of memory cells begins by providing a semiconductor substrate having partially completed DRAM devices. The substrate is single-crystal-silicon doped with a P type conductive dopant, such as boron (B). Shallow trench isolation (STI) regions are formed surrounding and electrically isolating an array of device areas for memory cells on the substrate. To form the STI shallow trenches are etched in the substrate, and the trenches are filled with an insulating material, such as silicon oxide (SiOx), and is polished back to the substrate to form a planar surface. These partially completed DRAMs also include word lines that extend over the device areas to form field effect transistors (FETs). Typically the FETs consist of a thin gate oxide on the device areas, and gate electrodes formed from a patterned polycide layer (word lines). The FETs also have source/drain areas, one on each side and adjacent to the FET gate electrodes.
A relatively thin conformal silicon nitride (Si3N4) barrier layer is formed over the device areas and over the STI regions to insulate the FET devices on the DRAM circuit. A first insulating layer is deposited on the substrate, and conducting first and second plug contacts are formed concurrently in the first insulating layer to contact the source/drain areas of the FETs. The conducting first plug contacts extend through the first insulating layer to the first source/drain areas for capacitors, and the conducting second plug contacts extend through the first insulating layer to the second source/drain areas for bit-line contacts. A second insulating layer is deposited, and first openings are formed in the second insulating layer aligned over the first conducting plug contacts.
A key feature of this invention is to deposit a first photoresist layer sufficiently thick to fill the first openings and to provide an essentially planar top surface over the substrate. The first photoresist layer is patterned to form second openings. Portions of the first photoresist are retained over the second plug contacts, and also extending over the edge of the first openings. The patterning is achieved by partially exposing the first photoresist through a photomask, and partially developing the photoresist. This patterning results in the first photoresist layer protecting the underlying second insulating layer over the second plug contacts (for the bit lines). The first photoresist in the second openings is recessed to expose the top surface of the second insulating layer. The exposed portions of the second insulating layer are then selectively and partially etched back to recess those portions below the top portions of the second insulating layer over the second plug contacts. The second insulating layer is recessed using plasma etching. The remaining first photoresist is removed, for example, by ashing. The capacitor bottom electrodes are formed in the first openings aligned over and contacting the first conducting plug contacts. The bottom electrodes are formed by depositing a conformal first conducting layer, such as a doped polysilicon layer, over the second insulating layer and in the first openings. To further increase the capacitance, a hemispherical silicon grain (HSG) layer can be formed on the polysilicon layer to increase the surface area. Then a second photoresist layer is deposited to fill the first openings and the recessed areas in the second insulating layer. The second photoresist is then partially exposed and developed to expose the HSG on the top surface of all of the second insulating layer, while the unexposed second photoresist remaining in the first openings protects the first conducting layer having the HSG layer on its surface. For example, the first conducting layer with its HSG layer is removed using plasma etching. The plasma etching is used to remove a portion of the exposed first conducting layer (HSG) on the sidewalls of the second insulating layer. The second photoresist is completely removed, exposing the patterned HSG in the first openings to complete the capacitor bottom electrodes. A thin conformal interelectrode dielectric layer (IDL) is formed on the bottom electrodes. For example, for the IDL a silicon oxide/silicon nitride/silicon oxide (ONO) layer can be formed on the bottom electrodes. Next a second conducting layer is deposited sufficiently thick to fill the first openings and to fill the recessed areas in the second insulating layer. The second conducting layer is polished back to the second insulating layer over the second plug contacts to form the capacitor top electrodes, which are auto-self-aligned to the second insulating layer over the second plug contacts. The auto-self-align results from the polish-back to the top surface of the second insulating layer. This sequence of process steps and novel structure provide an improved overlay margin between the capacitor and the bit-line contacts that are formed next. A third insulating layer is deposited to electrically insulate the capacitor top electrodes. Third openings for bit-line contacts are etched in the third insulating layer and in the second insulating layer aligned over and etched to the second plug contacts. A third conducting layer is deposited to fill the third openings and is polished or etched back to form bit-line contacts. A fourth conducting layer is deposited and patterned to form bit lines over and contacting the bit-line contacts to complete the array of novel memory cells for the DRAM device.